Mobile devices such as smartphones, laptops and iPads demand ultra-low power and instant-ON (ION) user experience after hibernation or power failure. The quick recovery of data from power down condition is of critical importance to provide ION experience. Conventional volatile systems require storage of processor states and cached data in off-chip non-volatile memory before hibernation and power down. The restoration is dominated by access latency from off-chip memory. Moreover, they cannot handle sudden power failures. With the introduction of non-volatile memory in lower level cache and memory, it is possible to restore the processor state quickly. However, the restoration is still contingent upon time to restart the pipeline.
State retentive sequential elements are gaining popularity as they can store the processor state before power outage, eliminating the need to restart the pipeline from scratch. This capability can potentially cut down the ON time drastically.
Several nonvolatile flip-flops (NVFFs) based circuitry designs have been widely investigated to this effect. NVFF saves the current logic state into its NV storage element before the power gating. After wake up, the data saved in the nonvolatile storage is restored to the flip-flop to resume normal operations.
A primary challenge in conventional NVFF design is the lack of support to handle sudden power outage. The NVFF circuitry shown in FIG. 1(a) incorporates two additional write driver circuitries to store data into magnetic tunnel junctions (MTJs). Nevertheless, this design is associated with increased area and power overhead. Although the NVFF circuitry shown in FIG. 1(b) provides a more power-efficient solution, incorporating the MTJs in the operational paths incurs delay overhead that limits the operating frequency of the flip-flops. A spin-Hall effect (SHE) based NVFF for energy-efficiency is shown in FIG. 1(c). However, a delay of about 30 ns for storing the data in MTJs makes it impractical for per-cycle data backup. Other previously proposed designs involve high delay and power overhead when resistances of the MTJs are sensed by a sense amplifier and forwarded to a slave circuitry.